The present invention relates generally to a semiconductor memory device, and more specifically to a semiconductor memory device including refresh test circuit for subjecting redundancy memory cells to a refresh test and a method for its test.
Due to a large bit capacity, a semiconductor memory device such as a dynamic random access memory (DRAM) is typically used as a main memory of a computer. A memory cell on a DRAM includes a data holding capacitor and a data transfer transistor. Each memory cell can store one bit of data by storing a quantity of electric charge as determined by the logic value of the stored data.
Over time, the stored electric charge can leak away from the memory cell and the integrity of the data can be compromised. The stored electric charge typically leaks away due to junction leakage current and subthreshold leakage current through the data transfer transistor.
In order to improve data integrity, refresh operations are performed to restore the electric charge stored in each memory cell.
A self refresh operation is one method used to restore the electric charge in each memory cell. In this case, the refresh is automatically executed for all the word lines of a memory cell array by using a counter having a predetermined count period and an internally generated address.
A CBR (CAS before RAS) refresh is another method used to restore the electric charge in each memory cell. In this case, a CBR command is input and an address counter provides the row address so that a word line is selected and memory cells are refreshed. CBR commands are continuously input until all word lines have been selected.
Each memory cell must be refreshed within a predetermined time period according to the specification of the DRAM. Thus, it is necessary that a refresh test is performed to determine if a DRAM satisfies the refresh period.
If the refresh test identifies a word line corresponding to a memory cell that fails the refresh test, a redundant word line can be used to replace the defective memory cell or row of memory cells. In this way, the overall manufacturing yield can be improved.
It is thus desirable that the same refresh test be performed for memory cells connected to the redundant word lines as is performed in the normal memory cells.
However, before fuse trimming (or blowing) is performed, an address of the redundant word line is not defined. This can make it difficult to perform a CBR refresh test for a memory cell that corresponds to the redundant word line in the same manner as an ordinary word line. This reason will now be described with reference to FIG. 1.
Referring now to FIG. 1, a block schematic diagram of a conventional DRAM is set forth and given the general reference character 100. Conventional DRAM 100 is illustrated from the viewpoint of performing a CBR refresh test.
Conventional DRAM 100 includes a x1 bit input/output construction and a memory cell region M having a 2 Mbit capacity and redundant word lines.
A command circuit 3 receives and decodes an external command and outputs command signals such as a CBR reference command signal RF, a RAS system activation signal ACTX, and a CAS system activation signal ACTY in accordance with the received command. A counter activation circuit 5 receives the CBR refresh command signal and outputs a CBR refresh counter activation signal ACBR accordingly.
CBR refresh counter 4 is activated by CBR refresh counter activation signal ACBR to count an input CBR command and output address counter signals (CNT0 to CNT11).
Address input circuit 1 shapes and translates externally received address signal (A0 to A11) and outputs internal address signals (IA0 to IA11).
X address buffer 2 multiplexes between internal address signals (IA0 to IA11) and address counter signals (CNT0 to CNT11) based upon RAS system activation signal ACTX to provide internal X address signals (XA0 to XA11).
X predecoder 6 decodes internal x address signals (XA0 to XA11) and outputs word line select signals (XP0 to XP4095). X decoder 7 selects and provides a boosted voltage to one of word lines (W0 to W4095) based upon word select signals (XP0 to XP4095).
Activation circuit 12 receives RAS system activation signal ACTX and outputs X address latch signal XLAT. X redundancy circuit 8 latches internal X address signals (XA0 to XA11) based upon X address latch signal XLAT and outputs internal redundant word line select signals (XRD0 to XRD63) in accordance with the value of internal X address signals (XA0 to XA11) and the value of fuse structures forming a ROM (read only memory) within X redundancy circuit 8. In this way, ordinary word lines can be replaced with redundant word lines.
In the redundancy test mode, redundancy test control circuit 11 activates a redundancy test mode activation signal TREDX. When redundancy test mode activation signal TREDX is activated, X redundancy control circuit 9 decodes internal x address signals (XA0 to XA11) to select one of redundant word line select signals (RXW0 to RXW63) and output a redundancy circuit use signal XRDV to deactivate of X predecoder 6.
X redundancy decoder 10 selects one of redundant word lines (RW0 to RW63) based on the redundant word line select signals (RXW0 to RXW63) and provides a boosted level on the one selected.
Y address buffer 13 outputs internal Y address signal (YA0 to YA8) based upon internal address signals (IA0 to IA8) when an active CAS system activation signal ACTY is received. Y-decoder 14 provides Y switch signals (Y0 to Y511) that select sense amplifiers corresponding to respective bit lines.
Memory cell region M is arranged to include 512 bit lines (bit line pairs), 4096 ordinary word lines and 64 redundant word lines. The bit lines are arranged perpendicular to and intersect the ordinary word lines and redundant word lines.
Referring now to FIG. 2, a block schematic diagram illustrating the arrangement of memory cell region M of conventional DRAM 100 is set forth.
Memory cell region M is divided into eight plates (P0 to P7). Each plate (P0 to P7) includes 512 word lines. For example, plate P0 includes word lines (W0 (#000) to W511 (#1FF)), plate P1 includes word lines (W512 (#200) to W1023 (#3FF)), etc. and plate P7 includes word lines (W3584 (#D00) to W4095 (#FFF)), where # indicates a word line address in hexidecimal notation.
Each plate (P0 to P7) includes 8 redundant word lines. For example, plate P0 includes redundant word lines (RW0 (#000) to RW7 (#007)), plate P1 includes redundant word lines (RW8 (#200) to RW15 (#207)), etc., and plate P7 includes redundant word lines (RW56 (#E00) to RW63 (#E07)), where # indicates a word line address in hexidecimal notation representing addresses represented by lower addresses (XA0, XA1, and XA2) and plate select addresses (XA9, XA10, and XA11).
Redundant word lines (RW0 to RW7) are used as replacement word lines for plate P0 and redundancy word lines (RW8 to RW15) are used as replacement word lines for plate P1, etc.
In plate P0, sense amplifier circuit 200 and bit lines (B0-0 to B0-511) are provided in a normal cell array NM and a redundant cell array RD. Also, in plate P1, sense amplifier circuit 201 and bit lines (B1-0 to B1-511) are provided in a normal cell array NM and a redundant cell array RD. Likewise, in plates (P2 to P7), respectively, there are sense amplifier circuits and 512 bit lines individually provided in a memory cell array NM and redundant cell array RD. Plates (P2 to P7) are not shown in detail in order to avoid unduly cluttering the figure.
In memory cell array NM, a memory cell NC is formed at predetermined intersections between word lines and bit lines.
In the same fashion, in redundant cell array RD, a redundant memory cell RC is formed at predetermined intersections between redundant word lines and bit lines.
A sense amplifier circuit (200 to 207) is provided for each plate (P0 to P7), respectively, to amplify data placed on bit lines when a word line is selected. A sense amplifier circuit (200 to 207) amplifies a differential voltage formed by a data signal and a reference potential to provide a logic data value.
A Y switch 21 selects an individual sense amplifier from a sense amplifier circuit 200 to 207) with Y switch signals (Y0 to Y511). In this way, data is input from an input/output buffer to a bit line during a write operation and data is output to an input/output buffer during a read operation.
The CBR refresh test for ordinary memory cells NC and redundant memory cells RC of conventional DRAM 100 will now be described.
Referring now to FIG. 3, a block diagram illustrating the CBR refresh counter 4 and X address buffer 2 is set forth.
When the CBR refresh test is performed for ordinary memory cells NC of memory cell array NM, address counter signals (CNT0 to CNT11) have a one-to-one correspondence with internal X address signals (XA0 to XA11), so that each time a CBR command is input, ordinary word lines are selected in a sequential order.
In the CBR refresh test for ordinary memory cell NC, data is written sequentially into memory cells connected with each word line. After a data holding time (pause time) has elapsed, for example 64 msec, data in the ordinary memory cells NC is read out sequentially and judged as to whether or not the correct data has been held.
Referring now to FIG. 4, a timing diagram illustrating the output of the CBR refresh counter 4 during a CBR refresh test is set forth. CBR refresh counter 4 counts the number of times the CBR command is received in synchronism with external clock CLK. Each time a CBR command is received, the CBR refresh counter 4 outputs incremented address counter signals (CNT0 to CNT11), which is output as internal X address signals (XA0 to XA11).
An address of the selected word line is represented by hexidecimal notation in the timing diagram of FIG. 4 in which the left digit includes the high order bits. For example, word line (#FF8) corresponds to word line W4088.
X predecoder 6 and X decoder 7 sequentially select 4096 word lines using the sequentially incremented address signals (XA0 to XA11). In this way, word lines (#000) to (#FFF) are sequentially selected one per clock cycle.
In the CBR refresh test for the memory cell array, word lines are selected sequentially in accordance with the period in which the CBR command is sequentially received with an external clock edge.
However, it is difficult to execute a refresh test on redundant memory cells RC connected to a redundant word line by using an address incremented in a CBR refresh counter 4 based on a CBR command in the same manner as the refresh test on ordinary memory cells NC.
As noted earlier, when a redundant word line replaces a normal word line, the redundant word line is selected using plate address signals and word line selecting address signals. Referring once again to FIG. 3, the plate selecting address signals are internal X address signals (XA9 to XA11), which are used to select any one of plates (P0 to P7). The word line selecting address signals are internal address signals (XA0 to XA8). However, there are only 8 redundant word lines in each plate, thus the redundant word lines only occupy 3 address spaces. Thus, only 3 internal X address signals (XA0 to XA2) are used to select a redundant word line in the refresh test.
For an address signal for selecting the redundant word line, internal X address signals (XA0 to XA2 and XA9 to XA11), respectively corresponding to address counter signals (CNT0 to CNT2 and CNT9 to CNT11), are input into X redundancy control circuit 9.
Accordingly, an address of the redundant word line is determined without the use of internal X address signals (XA3 to XA8). Thus, these addresses are not used when executing a refresh test on the redundant word lines. As noted, the hexidecimal address of redundant word lines in plate P0 is RW0 (#000) to RW7 (#007). In plate P1, the hexidecimal address of redundant word lines jump to RW8 (#200) to RW15 (#207). Thus, it can be seen that the addresses are not sequential when progressing from redundant word lines in one plate to redundant word lines in an adjacent plate.
Referring now to FIG. 5, a timing diagram illustrating the selection of the redundant word lines in conventional DRAM 100 when executing a refresh test of the redundant memory cells.
In the refresh test, internal X address signals (XA0 to XA11) are sequentially incremented. However, as noted only X address signals (XA0 to XA2 and XA9 to XA11) are used to select a redundant word line. Initially redundant word lines (RW0 to RW7) are sequentially selected. However, because CBR refresh counter 4 sequentially increments the address counter output signals (CNT0 to CNT11), redundant word lines (RW0 to RW7) are repeatedly sequentially selected until X address signal XA9 is incremented and plate P1 is selected. In this case, redundant word lines (RW0 to RW7) are repeatedly sequentially selected 26=64 times. Once plate P1 is selected the repetitive selection cycle is repeated for redundant word lines (RW8 to RW15). This will be continued until X address signal XA9 is changed back to zero and X address signal XA10 becomes a one, i.e., 64 times.
When the CBR refresh counter output is used for selection of a redundant word line as described above, redundant word lines (RW0 to RW55) are repeatedly refreshed 64 times each before redundant word lines (RW56 to RW63) are selected by the uppermost order addresses.
In a CBR refresh test using the conventional circuit as illustrated in conventional DRAM 100, lower order redundant word lines are selected 64 times before the upper order redundant word lines are selected. This can impact the test time and reduce test efficiency.
Also, because each redundant word line is refreshed many times, the refresh test may not have the same refresh period tested as in the case of the ordinary word line. This can affect the reliability of the refresh test results. Many manufacturers may not perform a CBR refresh test on redundant memory cells. Reasons may include complexity and inaccuracy of test results.
However, when a manufacturer selects not to perform a CBR refresh test on redundant memory cells, data holding time in the redundant memory cells are not confirmed until the redundant word line is used to replace an already known defective cell or cells. Once the fuse in a redundant word line decoder is programmed, the replacement is typically permanent. Thus, if a redundant word line that includes redundant memory cells that do not meet the required data holding time is used to replace a defective ordinary word line, then the semiconductor memory device may be rejected. In this case, the semiconductor memory device may have been a saleable product had a redundant word line that had redundant memory cells with sufficient data holding time been used instead. Thus, by performing a CBR refresh test on redundant memory cells, production yield may be decreased.
In order to address these problems, Japanese Patent Application No. Hei 10-62180 (JPA 10-62180) discloses a method for shortening the refresh cycle for a redundant word line in a semiconductor memory device. Thus, a redundant word line that does not meet the required data holding time may still properly function in a good product. This method shortens the cycle time of the refresh of the redundant word line instead of performing a test of the hold time functionality of the redundant memory cells.
This approach is problematic because a product that may include redundant memory cells having a reduced data holding time can be introduced into commerce. This product may have reduced reliability over time when it is continuously used.
Also, because the refresh periods of the ordinary memory cells differ from the redundant memory cells, a circuit is required for adjusting the timing of refreshing. This can cause the refresh control circuit to become complicated.
In light of the above discussion, it would be desirable to provide a semiconductor memory device where a refresh test, such as a CBR refresh test, on redundant memory cells is achieved in a similar fashion as the ordinary memory cells. It would also be desirable to provide the semiconductor memory device with excellent production efficiency and high reliability where the refresh test on redundant memory cells is achieved in a similar fashion as the ordinary memory cells. It would also be desirable to provide a method for the refresh test of the semiconductor memory device.
A semiconductor memory device and method for its test according to the present embodiments may include a CBR (CAS before RAS) refresh test achieved by inputting a CBR command for every redundant word line to be selected. In this way, redundant word lines may be sequentially selected without repetition until all the redundant word lines have been selected. By doing so, an accurate determination of the refresh period may be obtained. A CBR refresh counter may be activated every time a control signal is received when a refresh test on redundant memory cells is performed. Redundant counter signals may be applied to a X address buffer. The X address buffer may select the redundant counter signals to sequentially select the redundant word lines when the redundant refresh test is performed.
According to one aspect of the embodiments, a semiconductor memory device may include a memory cell array including a plurality of normal word lines and a plurality of redundant word lines. Each of the plurality of redundant word lines may be programmable to replace a defective one of the plurality of normal word lines. A test circuit may generate redundant word line selection signals so that the plurality of redundant word lines may be sequentially selected without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines have been selected.
According to another aspect of the embodiments, the test circuit may include a counter for generating an address by executing a counting operation every time a count command is received when normal word lines are selected. The test circuit may also include a redundancy counter for generating a redundant address by executing counting every time a cont command is received when redundant word lines are selected.
According to another aspect of the embodiments, the count command may be a CBR command and the semiconductor memory device may be a dynamic random access memory.
According to another aspect of the embodiments, the test circuit may include a counter incrementing an address when a count command is received. The test circuit may also include an address buffer that may rearrange the order of the address depending on whether a redundant word line or a normal word line is selected.
According to another aspect of the embodiments, the address buffer may include a selector for switching the order of the address when a redundant test signal is activated.
According to another aspect of the embodiments, the semiconductor memory device may be a dynamic random access memory. The test circuit may receive a redundant test signal. The redundant test signal may be activated when a redundant refresh test command is received.
According to another aspect of the embodiments, method for performing a refresh test in a semiconductor memory device having a plurality of normal word lines and a plurality of redundant word lines may include the steps of generating an address wherein a test address output circuit may sequentially generate the address for each normal word line, sequentially activating the plurality of normal word lines based on the address generated to refresh memory cells electrically connected to the activated normal word line, generating a redundant address wherein the test address output circuit may sequentially generate the redundant address for each redundant word line, and sequentially activating the plurality of redundant word lines based on the redundant address generated to refresh redundant memory cells electrically connected to the activated redundant word line without a repeat activation of any of the plurality of redundant word lines until all of the plurality of redundant word lines have been activated.
According to another aspect of the embodiments, generating the address may include counting every time a count command is received to sequentially generate the address for each normal word line. Generating the redundant address may include counting every time a count command is received to sequentially generate the redundant address for each redundant word line.
According to another aspect of the embodiments, the count command may be a CBR command. The semiconductor memory device may be a dynamic random access memory.
According to another aspect of the embodiments, the step of generating the redundant address may include changing the way counter outputs are mapped as compared to the step of generating the address.
According to another aspect of the embodiments, changing the way the counter outputs are mapped may include switching the order of counter outputs with a selector when one of the plurality of redundant word lines is activated.
According to another aspect of the embodiments, changing the way counter outputs are mapped may include generating a redundancy test signal.
According to another aspect of the embodiments, the refresh test may be performed before programming redundancy.
According to another aspect of the embodiments, a semiconductor memory device may include a memory cell array including a plurality of memory cell plates. Each memory cell plate may include a plurality of normal word lines and a plurality of redundant word lines. Each of the plurality of redundant word lines may be programmable to replace a defective one of the plurality of normal word lines. A test circuit may generate redundant word line selection signals so that the plurality of redundant word lines may be sequentially selected in each plate without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines in the plurality of plates have been selected.
According to another aspect of the embodiments, the plurality of plates may include a first plate and a second plate. The test circuit may be responsive to an externally applied selection command to generate the redundant word line selection signals. When a last one of the plurality of the redundant word lines in the first plate have been selected, one of the plurality of redundant word lines in the second plate may be selected on the subsequent selection command.
According to another aspect of the embodiments, the selection command may be a CBR command received synchronously with an external clock signal. The semiconductor memory device may be a dynamic random access memory.
According to another aspect of the embodiments, the test circuit may include a counter for generating an address by executing a counting operation every time a selection command is received when normal word lines are selected. The test circuit may also include a redundancy counter for generating a redundant address by executing counting every time the selection command is received when redundant word lines are selected.
According to another aspect of the embodiments, the test circuit may include a counter incrementing an address when a selection command is received and an address buffer rearranging the order of the address depending on whether a redundant word line or a normal word line is selected.
According to another aspect of the embodiments, the address buffer may include a selector for switching the order of the address when a redundant test signal is activated.
According to another aspect of the embodiments, the test circuit may receive a redundant test signal that may be activated when a redundant refresh test command is received.